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d1306hkim 20060911-s00004 no.a0139-1/26 ver.1.08 LC87F40C8A overview the sanyo LC87F40C8A is a closed caption tv controlling 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 71ns, inte grates on a single chip a number of hard ware features such as 128k-byte flash rom (size-variable program rom and cgrom), 2048-byte ram, 1024-byte cgram, 704 10-bit crt display ram, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters, two 8-bit timers with a pr escaler, a base timer serving as a time-o f-day clock, a high-speed clock counter, a synchronous sio interface (w ith automatic block transmission/reception capabilities), two channels of asynchronous/ synchronous sio interface (bus mode selectable), a uart inte rface (full duplex), an 8-bit 8-channel ad converter, one 14-bit pwm channel, three 8-bit pwm channels, a closed captio n data slicer, closed capti on compatible osd, a system clock frequency divider, rom correction function, an on-chip debugger, and onboard programming facilities. features ? flash rom 128k bytes ? 95k- to 110k-byte program rom (size variable) ? 16k- to 31k-byte character generator rom (size variable) ? runs on a 5v single source and permits onboard programming. ? block erasable in 128 byte units. ? permits 100 programming operations. ? internal ram ? general-purpose ram: 2k bytes ? character generator ram: 1k bytes ? crt display ram: 704 10 bits ? rom correction ram: 256 bytes ordering number : ena0139 cmos ic internal 128k-byte from (rom/cgrom), 2048 byte ram, 1024-byte cgram, and 704 10-bit crt display ram 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F40C8A no.a0139-2/26 ? minimum bus cycle time ? 71 ns (14.1mhz) note: the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time ? 212 ns (14.1mhz) ? osd ? screen size : 36 characters 16 lines ? display ram size : 704 words (1 word=10 bits) display area : 36 words 16 lines control area : 8 words 16 lines ? font types : 16 32 font, 512 types (16 cgram fonts, including 4 fixed fonts) an arbitrary number of charac ters can be generated as 16 17 or 8 9 font characters. ? display colors : 4096 colors character text, background, borders, and full background can be displayed. ? display mode specifiable on a line basis. normal, 4-color pixel map, 16-color pixel map, and caption text modes ? vertical display start line and horizontal display start position specifiable on a line basis. ? shutter function (specifying the display start or stop line) and scroll functions specifiable on a line basis. ? horizontal character sp acing (9 to 16 dots) *1 and vertical character spacing (1 to 32 dots) specifiable on a line basis. ? character size selectable from 16 character sizes on a line basis *1 . (horizontal vertical) = (1 1), (1 2), (2 1), (2 2), (2 4) (4 2), (4 4), (4 8), (1.5 1), (1.5 2) (3 1), (3 2), (3 4), (6 2), (6 4), (6 8) ? cursor display function (4/16 pixel colors) ? multilayer display ? full screen display area specifiable. ? osd clock selectable (normal speed mode/high speed mode/external input) ? interlace/progressive scan selectable *1: the supported range varies depending on the active display mode. refer to the user's guide for details. ? data slicer function (closed caption format) ? extracts closed caption data and xds data. ? ntsc/pal selectable and line specifiable. ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1-bit units 41 (p1n, p2n, p3n, p70 to p73, p8n, pc0 to pc4) ports whose i/o direction can be designated in 4-bit units 8 (p0n) ? timers ? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable pr escaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler + with an 8-bit prescal er 8-bit timer/counter mode 1: 6-bit timer/counter with an 8-bit prescaler ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes
LC87F40C8A no.a0139-3/26 ? high-speed clock counter 1) can count clocks with a maximum clock rate of 28.2mhz (at a main clock of 14.1mhz). 2) can generate output real-time. ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) ? sio1: 8-bit asynchr onous/synchronous serial interface (bus mode 1 system) mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio6: 8-bit asynchr onous/synchronous serial interface (bus mode 2 system) mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? uart ? full duplex ? 7/8/9 data bits selectable ? 1 stop bit ? built-in baudrate generator ? ad converter: 8 bits 8 channels ? pwm: 14-bit pwm 1 channel 8-bit pwm 3 channels ? remote control receiver circuit (shari ng with p73, int3, and t0in pins) ? noise rejection function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time)
LC87F40C8A no.a0139-4/26 ? interrupts ? 21 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l 4 0001bh h or l int3/base timer 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/uart1 receive 8 0003bh h or l sio1/uart1 transmit/data slicer/sio6 9 00043h h or l adc/vertical sync (vs)/scan line 10 0004bh h or l port 0/t4/t5 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 1024 levels maximum (the stack is allocated in ram.) ? oscillation circuits ? rc oscillation circuit (internal) : for system clock ? vco oscillation circuit (internal) : for system clock generation and crt display ? crystal oscillation circuit : for low-speed sy stem clock, base timer, and pll reference ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 212ns, 424ns, 848ns, 1.7 s, 3.4 s, 6.8 s, 13.6 s, 27.1 s, and 54.3 s (at a main clock rate of 14.1mhz). ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the vco, rc, and crystal oscillators automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the lower level. (2) setting at least one of the int0, int1, and int2 pins to the specified level (3) having an interrupt source established at port 0 ? rom correction function ? executes the correction program on detection of a match with the program counter value. ? correction program area size: 256 bytes (4 vector addresses) ? onchip debugger ? supports software debugging with the ic mounted on the target board ? package form ? qip64e(14 14): lead-free type ? dip64s(600mil): lead-free type ? development tools ? onchip debugger interface board: tcb87 (type b)
LC87F40C8A no.a0139-5/26 package dimensions unit : mm (typ) 3159a package dimensions unit : mm (typ) 3300 sanyo : qip64e(14x14) 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 116 17 32 33 48 49 64 sanyo : dip64s(600mil) 57.2 0.5 0.95 (1.01) 1.78 (4.25) 3.8 5.1max 0.51min 13.8 15.24 0.2 1 32 64 33
LC87F40C8A no.a0139-6/26 pin assignments sanyo : qip64e(14 14) ?lead-free type? p14/pwm a p15/pwmb p16/pwmc p17/pwmd bl1 b g r hsb vsb v ss 1 xt1 xt2 v dd 1 resb filt p13 p12/sck0 p11/si0/sb0 p10/so0 v dd 2 v ss 2 p27/bl2 p26/osdcki p25/urx p24/utx p23 p22/sck1 p21/si1/sb1 p20/so1 p07 p06 p05 p04 p03 p02 p01 p00 pc4 pc3 pc2 pc1 pc0 p37 p36 p35 p34/sck6 p33/sb6 cvin p70/int0/tolcp p71/int1/t0hcp p72/int2/t0in p73/int3/t0in p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p30/so6 p31/si6/sb6 p32/sck6 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 LC87F40C8A 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 top view
LC87F40C8A no.a0139-7/26 sanyo : dip64s (600mil) ?lead-free type? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 r g b bl1 p17/pwmd p16/pwmc p15/pwmb p14/pwma p13 p12/sck0 p11/si0/sb0 p10/so0 v dd 2 v ss 2 p27/bl2 p26/osdcki p25/urx p24/utx p23 p22/sck1 p21/si1/sb1 p20/so1 p07 p06 p05 p04 p03 p02 p01 p00 pc4 pc3 hsb vsb v ss 1 xt1 xt2 v dd 1 resb filt cvin p70/int0/t0lcp p71/int1/t0hcp p72/int2/t0in p73/int3/t0in p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p30/so6 p31/si6/sb6 p32/sck6 p33/sb6 p34/sck6 p35 p36 p37 pc0 pc1 pc2 LC87F40C8A top view
LC87F40C8A no.a0139-8/26 system block diagram interrupt control standby control ir pla clock generator vco rc x'tal bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 timer 4 timer 5 port 2 port 3 port 7 port c alu flash rom pc acc b register c register psw rar ram stack pointer watchdog timer pwm int0 to int3 noise filter base timer adc port 8 rom correct onchip debugger pll sio6 data slicer uart osd cgrom vram
LC87F40C8A no.a0139-9/26 pin description pin name i/o description option v ss 1 v ss 2 - - power supply pin no v dd 1 v dd 2 - + power supply pin no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units. ? hold reset input ? port 0 interrupt input yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p14: pwma output p15: pwmb output p16: pwmc output p17: pwmd output yes port 2 p20 to p27 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20: sio1 data output p21: sio1 data input/bus i/o p22: sio1 clock i/o p24: uart transmit p25: uart receive p26: external osd clock input p27: fast blanking 2 control signal output yes port 3 p30 to p37 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p30: sio6 data output p31: sio6 data input/bus i/o p32: sio6 clock i/o p33: sio6 bus i/o p34: sio6 clock i/o onchip debugger pins: dbgp0 to dbgp2 (p35 to p37) yes continued on next page.
LC87F40C8A no.a0139-10/26 continued from preceding page. pin name i/o description option port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p71: int1 input/hold reset i nput/timer 0h capture input p72: int2 input/hold reset input/time r 0 event input/timer 0l capture input p73: int3 input (with noise filter input)/t imer 0 event input/timer 0h capture input interrupt acknowledge type rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable p70 to p73 i/o no port 8 p80 to p87 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? shared pins ad converter input: an0 (p80) to an7 (p87) no port c pc0 to pc4 i/o ? 5-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. yes res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin no xt2 i/o ? 32.768khz crystal oscillator output pin no filt output ? internal pl filter pin no cvin input ? video input pin no vs input ? vertical sync input pin no hs input ? horizontal sync input pin no r output ? red (r) rgb video output pin no g output ? green (g) rgb video output pin no b output ? blue (b) rgb video output pin no bl1 output ? fast blanking 1 control output pin no
LC87F40C8A no.a0139-11/26 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain no 1 cmos programmable p10 to p17 p20 to p27 p30 to p37 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable p80 to p87 - no nch-open drain no 1 cmos programmable pc0 to pc4 1 bit 2 nch-open drain programmable note 1: programmable pull-up resistors for port 0 are controlled in 4 bit units (p00 to 03, p04 to 07). *1 connect the ic as shown below to minimize the noise input to the v dd 1 pin. be sure to electrically short the v ss 1 and v ss 2 pins . on-board writing system the LC87F40C8A has the on-board writing system. the program is renewable by using sanyo flash on-board system after the lsi has been inst alled on the application board. this system has to connect the 6 pins (v dd , v ss , res , communication pins) with the interface board of sanyo flash on-board system. it is necessary that the pins to be used for the rewriting syst em should be able to be separated from the application board properly. ? the loader program must be written into the rom to use on-board writing system. the loader program should be written into the rom before the lsi has been installed on the board by the general purpose prom programs. when the option setting selects the this system to use, the loader program automatically links on the user program linking. please ask to our sales persons before using on-board writing system. power supply lsi v dd 1 v dd 2 v ss 2 v ss 1
LC87F40C8A no.a0139-12/26 method of how to rewrite it in flash programmer/ sanyo flash writing tool (sfws) when reading or writing data to the LC87F40C8A, flash programmer of our recommendation or sanyo flash writing tool (sfws) is used. in both cases, exclusiv e conversion board (w87f40c8d, w87f40c8q) is needed. (1) flash programmer of our recommendation single word write manufacture name of device ve rsion applicable device (code) data protection setting after write operation flash support group co. (the former ando electric) af9708 rev02.35 sanyo LC87F40C8A (3b21c) protected write multiple words manufacture name of device ve rsion applicable device (code) data protection setting after write operation flash support group co. (the former ando electric) af9723 + af9833 rev01.83 sanyo LC87F40C8A (3b21c) protected ? the LC87F40C8A does not support a silicon signature feature. do not use the feature (automatic device type selection) when programming this device. ? to avoid erasing the program, confirm the setting of the protection for activating the written program before using. ? it can?t be written with device code 29ee010 (2) sanyo flash writing tool (sfws) pc is connected with writer unit (skk) by usb cable and it uses it. (3) exclusive writing conversion board ? w87f40c8d: dip64s purpose ? w87f40c8q: qip64e purpose when using the conversion board, all of the jumper sw must be set to the off position. if set to the on position, read/write operations will not perform correctly. pin 1 of the conversion board should be located as indicated below. w87f40c8d: when viewing from the edge closest to jumper sw, pin 1 is located on the lower right of both the chip and conversion board. w87f40c8q: when viewing from the edge closest to jumper sw, pin 1 of the chip is located on the upper right while pin 1 of the conversion board is located on the lower right. 1pin w87f40c8q 1pin w87f40c8d
LC87F40C8A no.a0139-13/26 absolute maximum ratings at ta = 25 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2 v dd 1=v dd 2 -0.3 +6.5 input voltage v i (1) xt1, res , hs, vs, cvin -0.3 v dd +0.3 output voltage vo(1) xt2, bl1, r, g, b filt -0.3 v dd +0.3 input/output voltage v io (1) ports 0, 1, 2, 3 ports 7, 8 port c -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3, c bl cmos output select per 1 applicable pin -10 ioph(2) ports 71 to 73 per 1 applicable pin -5 peak output current (note 1-1) ioph(3) r, g, b osd is digital mode per 1 applicable pin -10 ioah(1) port 7 total of all applicable pins -25 ioah(2) ports 0, 2, 3, c total of all applicable pins -25 high level output current total output current ioah(3) ports 1 r, g, b, bl total of all applicable pins -25 iopl(1) ports 0, 1, 2, 3, c bl per 1 applicable pin 20 iopl(2) ports 7, 8 per 1 applicable pin 10 peak output current (note 1-1) iopl(3) r, g, b osd is digital mode per 1 applicable pin 20 ioal(1) ports 7, 8 total of all applicable pins 20 ioal(2) ports 0, 2, 3, c total of all applicable pins 45 low level output current total output current ioal(3) ports 1 r, g, b, bl total of all applicable pins 45 ma qip64e(14 14) 390 allowable power dissipation pd max dip64s(600mil) ta=-10 to +70 c 880 mw operating ambient temperature topr -10 +70 storage ambient temperature tstg -55 + 125 c note 1-1: the average current per ap plicable pit must not exceed 10ma.
LC87F40C8A no.a0139-14/26 allowable operating conditions at ta = -10 c to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit operating supply voltage v dd (1) v dd 1=v dd 2 0.211 s tcyc 200 s 4.5 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2 ram and register contents sustained in hold mode 2.0 5.5 v ih (1) ports 0, 1, 2, 3 p71 to p73, 8, c p70 port input/ interrupt side hs, vs 4.5 to 5.5 0.3v dd +0.7 v dd v ih (2) port 70 watchdog timer side 4.5 to 5.5 0.9v dd v dd high level input voltage v ih (3) xt1, res 4.5 to 5.5 0.75v dd v dd v il (1) ports 0, 1, 2, 3 p71 to p73, 8, c p70 port input/ interrupt side hs, vs 4.5 to 5.5 v ss 0.1v dd +0.4 v il (2) port 70 watchdog timer side 4.5 to 5.5 v ss 0.15v dd +0.4 low level input voltage v il( 3) xt1, res 4.5 to 5.5 v ss 0.25v dd v cvin input amplitude vcvin cvin 5.0 1vp-p -3db 1vp-p 1vp-p +3db vp-p tcyc(1) (note 2-1) all functions 4.5 to 5.5 0.211 0.212 0.213 s instruction cycle time tcyc(2) (note 2-1) except for osd and data slicer functions 4.5 to 5.5 0.211 200 s fexos(1) scon1=0 14.28 15.44 external osd clock frequency fexos(2) p26/osdcki duty50 5% of external osd clock (note 2-3) scon1=1 4.5 to 5.5 28.56 30.88 mhz fmvco1 internal vco1 oscillator 4.5 to 5.5 14.08 14.15 14.22 cksel0=0 14.28 14.75 15.44 fmvco2 internal vco2 oscillator (note 2-3) cksel0=1 4.5 to 5.5 28.56 29.5 30.88 fmrc internal rc oscillator 4.5 to 5.5 0.3 1.0 2.0 mhz oscillation frequency range (note 2-2) fsx'tal xt1, xt2 32.768khz crystal oscillation mode see fig. 1. 4.5 to 5.5 32.768 khz note 2-1: relationship between tcyc and oscillation frequency is 3/fmvco1 at a division ratio of 1/1 and 6/fmvco1 at a division ratio of 1/2. note 2-2: see table 1 for the oscillation constants note 2-3: scan1 is hsync frequency switch bit. cksel0 is osd clock frequency switch bit. (refer to the lc874000 user's manual for details.)
LC87F40C8A no.a0139-15/26 electrical characteristics at ta = -10 c to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3 ports 7, 8 port c output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 4.5 to 5.5 1 high level input current i ih (2) res , hs, vs v in =v dd 4.5 to 5.5 1 i il (1) ports 0, 1, 2, 3 ports 7, 8 port c output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 4.5 to 5.5 -1 low level input current i il (2) res , hs, vs v in =v ss 4.5 to 5.5 -1 a v oh (1) ports 0, 1, 2, 3, 8 port c i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) p71 to p73 i oh =-0.4ma 4.5 to 5.5 v dd -1 v oh (3) r, g, b i oh =-5ma 4.5 to 5.5 v dd -1 high level output voltage v oh (4) bl1, p27/bl2 i oh =-5ma when bl2 is output 4.5 to 5.5 v dd -1 i ol =10ma 4.5 to 5.5 1.5 v ol (1) ports 0, 1, 2, 3, 8 port c i ol =1.6ma 4.5 to 5.5 0.4 v ol (2) port 7 i ol =1ma 4.5 to 5.5 0.4 v ol (3) r, g, b i ol =5ma 4.5 to 5.5 0.4 low level output voltage v ol (4) bl1, p27/bl2 i ol =5ma when bl2 is output 4.5 to 5.5 0.4 v pull-up resistance rpu ports 0, 1, 2, 3, 7 ports 8, c v oh =0.9v dd 4.5 to 5.5 15 40 70 k ? hysteresis voltage vhys res ports 1, 2, 3, 7 hs, vs 4.5 to 5.5 0.35 v bus terminal short circuit resistance for internal communication rbs ? p31, p33 ? p32, p34 130 300 ? pin capacitance cp all pins for pins other than that under test: v in =v ss f=1mhz ta=25 c 4.5 to 5.5 10 pf
LC87F40C8A no.a0139-16/26 serial i/o characteristics at ta = -10 c to +70 c, v ss 1 = v ss 2 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit period tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 5. 1 tsckha(1a) ? continuous data transmission/ reception mode ? osd inactive ? see fig. 5. ? (note4-1-2) 4 input clock high level pulse width tsckha(1b) sck0(p12) ? continuous data transmission/ reception mode ? osd active ? see fig. 5. ? (note4-1-2) 4.5 to 5.5 6 period tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) ? cmos output selected ? see fig. 5. 1/2 tsck tsckha(2a) ? continuous data transmission/ reception mode ? osd inactive ? see fig. 5. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc serial clock output clock high level pulse width tsckha(2b) sck0(p12) ? continuous data transmission/ reception mode ? osd active ? see fig. 5. 4.5 to 5.5 tsckh(2) +2tcyc tsckh(2) +(16/3) tcyc tcyc data setup time tsdi(1) 0.03 serial input data hold time thdi(1) si0(p11), sb0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 5. 4.5 to 5.5 0.03 tdd0(1) ? continuous data transmission/ reception mode ? (note4-1-3) (1/3)tcyc +0.05 input clock tdd0(2) ? synchronous 8-bit mode ? (note4-1-3) 1tcyc +0.05 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11), (note4-1-3) 4.5 to 5.5 (1/3)tcyc +0.05 s note4-1-1: this standard value is a theory value. be sure to ensure the margin according to busy condition. note4-1-2: when using the serial clock in continuous data transmission/reception mode, the time to the first falling edge of the serial clock after it sets siorun in ?h? state is more extended than tsclkha. note4-1-3: it is defined for the falling edge of sioclk. in open drain output, it is defined as the time to start the output change. see fig. 5.
LC87F40C8A no.a0139-17/26 2. sio1, 6 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit period tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p22), sck6(p32, p34) see fig. 5. 4.5 to 5.5 1 period tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p22), sck6(p32, p34) ? cmos output selected ? see fig. 5. 4.5 to 5.5 1/2 tsck data setup time tsdi(2) 0.03 serial input data hold time thdi(2) si1(p21), sb1(p21), si6(p31), sb6(p31, p33), ? must be specified with respect to rising edge of sioclk. ? see fig. 5. 4.5 to 5.5 0.03 serial output output delay time tdd0(4) so1(p20), sb1(p21), so6(p30), sb6(p31, p34) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 5. 4.5 to 5.5 1/3tcyc +0.05 s note4-2-1: this standard value is a theory value. be sure to ensure the margin according to busy condition.
LC87F40C8A no.a0139-18/26 pulse input conditions at ta = -10 c to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), ? interrupt source flag can be set. ? event inputs for timers 0 and 1 are enabled. 4.5 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled 4.5 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 4.5 to 5.5 256 tcyc tpil(5) res resetting is enabled. 4.5 to 5.5 200 high/low level pulse width tpih(6) tpil(6) hs , vs ? display position controllable (note) ? the active edge of hs and vs must be apart at least 1 tcyc. ? see fig. 7. 4.5 to 5.5 1 s falling time tthl hs see fig. 7. (note 5-1) 4.5 to 5.5 100 ns external osd clock input frequency toscki osdcki(p26) see fig. 8. 4.5 to 5.5 10 ns note 5-1: when the falling edge of hs is affected by the noise, the start position of osd can slip off. note that the signal lines with rapid state change or with large current should be allocated away from hs line. ad converter characteristics at ta = -10 c to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 4.5 to 5.5 8 bit absolute accuracy et (note 6-1) 4.5 to 5.5 1.5 lsb ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 4.5 to 5.5 13.50 (tcyc= 0.422 s) 97.92 (tcyc= 3.06 s) conversion time tcad ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 4.5 to 5.5 13.50 (tcyc= 0.211 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 4.5 to 5.5 v ss v dd v iainh vain=v dd 4.5 to 5.5 1 analog port input current iainl an0(p80) to an7(p87) vain=v ss 4.5 to 5.5 -1 a note 6-1: the quantization error ( 1/2lsb) is excluded from th e absolute accuracy value. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.
LC87F40C8A no.a0139-19/26 analog mode rgb characteristics at ta = -10 c to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions min typ max unit output resistance r, g, b v dd =5.0v 2.5 k ? analog output deflection varo r, g, b v dd =5.0v 20 % time seting tst r, g, b 70%dc level 10pf load 50 ns 1/16(v) 2/16(v) 3/16(v) 4/16(v) tst varo varo 70%vp-p 30%vp-p vp-p
LC87F40C8A no.a0139-20/26 consumption current characteristics at ta = -10 c to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit iddop(1) ? fmx'tal=32.768khz crystal oscillation mode ? system clock set to main clock vco ? osd vco active ? internal rc oscillator inactive ? 1/1 frequency division ratio ? osd is analog mode ? dsl active 4.5 to 5.5 36 58 ma iddop(2) ? fmx'tal=32.768khz crystal oscillation mode ? system clock set to main clock vco ? osd vco active ? internal rc oscillator inactive ? 1/1 frequency division ratio ? osd is digital mode ? dsl active 4.5 to 5.5 28 47 ma normal mode current drain (note 7-1) iddop(3) ? fmx'tal=32.768kh z crystal oscillation mode ? system clock set to 32.768khz ? main clock and osd vcos inactive ? internal rc oscillator inactive ? 1/2 frequency division ratio 4.5 to 5.5 100 300 a iddhalt(1) halt mode ? fmx'tal=32.768khz crystal oscillation mode ? system clock set to main clock vco ? osd vco active ? internal rc oscillator inactive ? 1/1 frequency division ratio 4.5 to 5.5 7 11 ma iddhalt(2) halt mode ? fmx'tal=32.768khz crystal oscillation mode ? system clock set to internal rc oscillator ? 1/1 frequency division ratio 4.5 to 5.5 600 1600 halt mode current drain (note 7-1) iddhalt(3) v dd 1 =v dd 2 halt mode ? fmx'tal=32.768khz cr ystal oscillation mode ? system clock set to 32.768khz ? main and osd vcos inactive ? internal rc oscillator inactive ? 1/2 frequency division ratio 4.5 to 5.5 75 200 a hold mode current drain iddhold v dd 1 hold mode ? all oscillators inactive 4.5 to 5.5 0.05 20 a note 7-1: the current drain valu e includes none of the currents that flow into the output transistors and internal pull-up resistors.
LC87F40C8A no.a0139-21/26 f-rom programming characteristics ta = +10 to +55 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? 128-byte programming ? erasing current included 4.5 to 5.5 25 ma programming time tfw(1) ? 128-byte programming ? erasing current included ? time for setting up 128-byte data is excluded. 4.5 to 5.5 22.5 ms uart (full duplex) op erating conditions at ta=-10 to +70 c , v ss 1=v ss 2=0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit transfer rate ubr p24, p25 4.5 to 5.5 16/3 8192/3 tcyc data length: 7/8/9 bits (lsb first) stop bits: 1 bit parity bits: none example of continuous 8-bit da ta reception mode processing (first transmit data=55h) example of continuous 8-bit da ta reception mode processing (first receive data=55h) transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit receive data (lsb first) ubr start of reception start bit stop bit end of reception
LC87F40C8A no.a0139-22/26 recommended oscillation circui t and sample characteristics the sample oscillation circuit characteristics in the table below is based on the following conditions: ? recommended circuit parameters are verified by an os cillator manufacturer using a sanyo provided oscillation evaluation board. ? sample characteristics are the result of the evaluation with the recommended circuit parameters connected externally. table 1. recommended oscillation circuit and sample characteristics (ta = -10 to +70c) recommended circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] operating supply voltage range [v] typ [s] max [s] remarks 32.768khz seiko epson c-002rx 18 18 open 620k 4.5 to 5.5 1.00 1.50 notes: the oscillation stabilizing time period is the time un til the vco oscillation for the internal system becomes stable after the following conditions. (see figure 3.) 1. the v dd becomes higher than the minimum operating voltage after the power is supplied. 2. the hold mode is released. the sample oscillation circuit characteristics may differ app lications. for further assistance, please contact with oscillator manufacturer with the following notes in your mind. ? since the oscillation frequency precision is affected by wiring capacity of th e application board, etc., adjust the oscillation frequency on the production board. ? the above oscillation frequency and the operating supply vo ltage range are based on the operating temperature of -10 c to +70 c. for the use with the temperature outside of the range herein, or in the application requiring high reliability such as car products, please consult with oscillator manufacturer. ? when using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with sanyo sales personnel. since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. ? the distance between the clock i/o terminal (xt1 terminal xt 2 terminal) and external parts should be as short as possible. ? the capacitors? v ss should be allocated close to the microcontroller?s gnd terminal and be away from other gnd. ? the signal lines with rapid state change or with large curr ent should be allocated away from the oscillation circuit. figure 1 recommended oscillation circuit figure 2 ac timing measurement point c1 rd c2 x?tal xt2 xt1 rf 0.5v dd
LC87F40C8A no.a0139-23/26 reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 3 oscillation stabilization timing power supply res interna rc oscillation vco1 xt1, xt2 operating mode reset time tmsvco tmsx?tal unpredictable reset instruction execution v dd operating v dd lower limit 0v internal rc oscillation hold reset signal vco1 xt1, xt2 state no hold reset signal hold reset signal valid tmsvco tmsx?tal hold halt
LC87F40C8A no.a0139-24/26 figure 4 reset circuit figure 5 serial i/o output waveforms figure 6 pulse input timing signal waveform 1 c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic?s operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk : datain : dataout : dataout : datain : sioclk : dataout : datain : sioclk : tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
LC87F40C8A no.a0139-25/26 figure 7 pulse input timing signal waveform 2 note: last transition of the t0scki must be saving constant. figure 8 pulse input timing signal waveform 3 note: the output impedance of the c-video side as vi ewed from the input of the noise filter must be 100 ? or less. figure 9 recommended cvin circuit note: place the components to be connected to the filt pin so that their trace length is minimum. figure 10 recommended filter circuit tpil(6) tpil(6) tthl 0.75v dd 0.25v dd more than 1 tcyc hs vs toscki hs osdcki toscki 200 ? c-video 1000pf 1 ? 1m ? 2.2 + -
LC87F40C8A no.a0139-26/26 ps this catalog provides information as of december, 2006. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qu ality high-reliability pr oducts, however, any and all semiconductor products fail or malfunction with some proba bility. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damag e to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products descr ibed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co .,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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